| 摘要 |
PROBLEM TO BE SOLVED: To shorten verification time and improve design quality by providing a bypass circuit of the sequential circuit in a test circuit inserted in between modules and matching a pattern for connection verification from an output terminal with a connecting input terminal. SOLUTION: A test selection signal inputting in a test circuit 20 is made '1' and the signals of output terminals OUT1 to OUT3 of a module A are connected to selector circuits SEL1 to SEL3. Also, a bypass selection signal inputting in a bypass circuit 10 is made '0', internal selection circuits SEL1' to SEL3' are connected to the selector circuits SEL1 to SEL3 not by way of a sequential circuit 201 and the signals from the output terminals OUT1 to OUT3 are directly connected to IN1 to IN4 of modules B and C. Thus, it is made possible to verify whether the input waveform patterns of input terminals corresponding to the modules B and C are the same or not and verify the justification of the connection and so the design quality can be improved. |
