SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To contemplate to eliminate a clock skew in a semiconductor integrated circuit device without augmenting the consumption power of the circuit device, by a method wherein the first output node of a delay adjusting circuit element connected with a signal source circuit unit is connected with a first logic circuit unit, and the second output node of a delay adjusting circuit element connected with the signal source circuit unit is connected with a second logic circuit unit. SOLUTION: Delay adjusting circuit elements 203 to 206, which respectively have a total of 80 ps element delays, are connected with a clock signal source cell 201 in 4-steps series. Interelement wirings 211 to 214 are connected with flip-flop cells via an output node of the element 204 and in a state that a difference between the wiring lengths of the interelement wirings is generated in the interelement wirings, the wiring 214 is connected with the first flip-flop cell 210 via an output node of the first delay adjusting circuit element 203, and the wiring 211 is connected with the second flip-flop cell 207 via an output node of the second delay adjusting circuit element 204. Similarly, the wiring 213 is connected with the third flip-flop cell 209 via an output node of the third delay adjusting circuit element 205, and the wiring 212 is connected with the fourth flip-flop cell 208 via an output node of the fourth delay adjusting circuit element 206.