发明名称 CLOCK DIVIDING DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To provide a clock dividing device which can optionally adjust the dividing ratio, duty and phase and can generate a dividing clock. SOLUTION: The count value of a counter 1 is compared with the Hi and Low set values inputted from the terminals 7 and 8 respectively. Then a synchronous RS flip-flop circuit 5 is controlled to acquire a divided clock that has the optional duty and phase. Meanwhile, the count value of the counter 1 is compared with the reset value inputted from a terminal 9 to control the resetting of the counter 1. Thus, a divided clock having an optional dividing ratio is obtained.</p>
申请公布号 JPH114162(A) 申请公布日期 1999.01.06
申请号 JP19970154983 申请日期 1997.06.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TERADA MITSUTAKA
分类号 G06F1/06;G06F1/08;H03K5/04;H03K5/156;H03K7/08;H03K23/64;(IPC1-7):H03K23/64 主分类号 G06F1/06
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