Method for preventing sub-threshold leakage in flash memory cells to achieve accurate reading, verifying, and fast over-erased Vt correction

摘要

The present invention provides a method for preventing sub-threshold leakage in flash EPROM cells during Vt repair, read and verify operations. The present invention prevents sub-threshold leakage by either biasing the floating gate voltage of non-selected cells to a level that is less than the sources voltage. This biasing is achieved by controlling the voltages applied to such non-selected cells bitline and wordline voltages, or by floating the non-selected sourcelines to electrically disconnect the sourcelines of the non-selected cells. This method allows fast and accurate Vt repair of cells while avoiding Vt degradation of non-erased and repaired cells due to subthreshold current leakage, as well as reduced sub-threshold leakage during read and verify operations.