| 摘要 |
A technique for improving the manufacturing yield of data processing memory. A memory array contains a known pattern of single-bit defects. Specifically, a first group of the memory cells contain flawless storage devices which are capable of being set to either of two possible stable states, i.e., a binary "1" or a binary "0." A second group of the memory cells contain the single-bit defects. These storage devices of the second group are capable of being set to only one of the two possible stable states. Before data is loaded into the memory, a coder codes the data such that bits to be loaded into the memory cells with bit defects match the state of the bit defect. The coder also generates code bits capable of decoding the coded data. A memory input-output circuit loads the code bits and the coded data blocks into the memory cells. When the memory input-output circuit accesses the memory, it passes the coded data blocks and the code bits to a decoder which uses the code bits to decode the data blocks. |
