| 摘要 |
The architecture of this invention makes multiple use of switched time-delay circuits to reduce the complexity of both series and parallel feed antenna arrays. Each time-delay circuit can give a delay that can be switched to values between 0 and 2d/c, where d is the inter-element spacing and c is the velocity of light. At the highest frequency of the series feed array, the elements are spaced by lambda /2 to avoid grating lobes and the maximum delay corresponds to 360 DEG of phaseshift. When the time-delays are set half way (d/c), the various lines feeding the elements of the array at the aperture have bias delays that make them all equal in length, thereby giving a broadside beam, independent of frequency. At the highest frequency, the switchable time delay gives some excess in available delay. If additional excess time-delay is needed it can be obtained by increasing the time delay circuit range. Insertion loss is proportional to the number of bits used. This could become high in large antennas, however, this loss may be compensated by the addition of two-way amplification in the branch lines with an appropriate bias length adjustment. Also the insertion loss may be reduced by dividing the array into subarrays which are then combined by a series feed combiner network.
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