发明名称 |
Logic synthesis method and system with intermediate circuit files |
摘要 |
An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction. The system includes a logic input device for inputting an old logic, an old circuit generated from the old logic and optimized to satisfy the design constriction, and a new logic partially changing from the old logic file, a logic synthesizing device for generating a first intermediate circuit file from the new logic file, a discriminating device for discriminating a common sub-circuit of the old circuit having an equivalent logic function and an uncommon sub-circuit of the first intermediate circuit having an inconsistent logic function, from the old circuit and the first intermediate circuit, a circuit updating device for generating a second intermediate circuit file by merging the common sub-circuit of the old circuit and the uncommon sub-circuit of the first intermediate circuit, and an optimizing device for optimizing the uncommon sub-circuit of the second intermediate circuit so as to satisfy the design constriction.
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申请公布号 |
US5856926(A) |
申请公布日期 |
1999.01.05 |
申请号 |
US19960599090 |
申请日期 |
1996.02.07 |
申请人 |
HITACHI, LTD.;HITACHI SOFTWARE ENGINEERING CO., LTD. |
发明人 |
MATSUMOTO, KAZUHIKO;SHINSHA, TAKAO;HAYASHI, NOBUYUKI;SAKAKI, HIROMOTO;TANDAI, MIYAKO;YAMADA, YASUNORI;NAKATA, TAKAHIRO;MORIWAKI, KAORU;KOSHISHITA, JUNJI |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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地址 |
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