| 摘要 |
<p>The procedure involves using a pre-charge stage for a bit line (B1) and a reference line (B2) for carrying the potential (Vb1,Vb2) of the lines to a reference potential (Vref) level which is different from the initial potential memorised in the cell (C11). A selection stage is used for the memory cell for producing a modification of the potential (Vb1) of the bit line (B1), thus creating an initial difference between the potentials of the bit line and the reference line. It also has a discharge stage for the bit line and the reference line, which have discharge currents running through them, and an output signal (OUT1) production stage representing the values of the output currents.</p> |
