| 摘要 |
<p>A multiplying circuit consists of a partial product adding circuit (10) and a final stage adding circuit (20), and serves to extract, as an operation result, high-order p bits (p < m + n) of a multiplication result obtained through multiplication of a binary multiplicand of m bits by a binary multiplier of n bits, wherein at least one of the partial product adding circuit (10) and the final stage adding circuit (20) comprises a sum generating circuit (11, 21) to execute addition of bits related directly to the multiplication result of the high-order p bits, and a carry generating circuit (12, 22) to execute only generation of a carry relative to low-order q bits (q = m + n - p). In this configuration, only the carry signal alone is needed with regard to the partial product of the low-order bits and the final stage addition, hence curtailing the number of required component elements and raising the operation speed correspondingly thereto. <IMAGE></p> |
