Computer system generating a processor interrupt in response to receiving an interrupt/data synchronizing signal over a data bus

摘要

A computer system having interrupts synchronized to data storage by having an interrupt data signal (interrupt packet) follow the path of the data to an interrupt receiver, which interrupts the processor to execute an interrupt service routine. Rather than having a dedicated interrupt line from a peripheral device to a processor, the peripheral device sends the interrupt across a bus from the peripheral to the processing unit via an interrupt receiver. The system can include a processor; a memory circuit in circuit communication with the processor; a peripheral device in circuit communication with the memory circuit via a bus; and an interrupt circuit in circuit communication with the peripheral circuit via the bus and in circuit communication with the processor via an interrupt bus; and wherein the peripheral device transmits data to the memory circuit across the bus and then transmits a predetermined interrupt data signal to the interrupt circuit across the bus; and wherein the interrupt circuit asserts an interrupt signal onto the interrupt bus to interrupt the processor responsive to receiving the predetermined interrupt data signal from the bus, thereby assuring that the processor is interrupted after the data is transmitted to the memory circuit.