Method and apparatus for identifying flip-flops in HDL descriptions of circuits without specific templates

摘要

A method and apparatus is disclosed for detecting edge-sensitive behavior from HDL descriptions of a circuit and inferring a hardware implementation of that behavior as a generalized edge-triggered D-type flip-flop with asynchronous set and clear inputs. The invention detects the edge-sensitive behavior from directed acyclic graphs (DAGS) that represent the individual signal nets of the circuit as affected by each process defined in the HDL description of the circuit. The invention then modifies each DAG to infer the asychronous control expressions and the data input expression necessary to control generalized flip-flop to emulate the behavior of the net represented by the DAG. The invention then creates a symbolic hardware implementation of the net's behavior using the D-type flip-flop and any combinational logic necessary to produced the inferred control signals. The symbolic hardware implementations for each net can then be optimized using well-known techniques, and a netlist generated therefrom for purposes of creating masks for manufacturing the circuit. The invention can be easily implemented within known symbolic simulator routines already capable of synthesizing level-sensitive behavior using combinational logic.