Low loss integrated circuit with reduced clock swing

摘要

PCT No. PCT/DE95/00335 Sec. 371 Date Sep. 24, 1996 Sec. 102(e) Date Sep. 24, 1996 PCT Filed Mar. 10, 1995 PCT Pub. No. WO95/26077 PCT Pub. Date Sep. 28, 1995The integrated circuit with a clock system, particularly a CMOS circuit with extensive pipelining, whereby an optimally low overall dissipated power is effected in that a clock driver circuit is provided with a specifically wired driver output stage that generates a clock supply voltage that corresponds to about half the value of a general supply voltage. A great reduction of the dissipated power can be achieved given relative slight sacrifices in the performance capability.