Synchronisation apparatus for packet transmission

摘要

The apparatus includes a shift register (11) with several buffers (BS1,BS2) which store standard data forming an input data signal. A model data extraction unit (12) extract L bit data from the stored data according to first to Kth models. A first comparator unit (16) compares all first to Kth extraction data with a synchronisation code (Cd) as indicator of a header (H) of a packet. A model selection part (23) selects and outputs one of the first to Kth extraction data as extraction signal (Dout). A state conversion control unit (18) controls the selection of the model selection unit in dependence on the existence of synchronous or asynchronous state.