发明名称 |
Clock signal switching method for telecommunication |
摘要 |
The method involves switching between a number of input clock signal (Clock1IN, Clock2In) with the same pulse-pause ratio. A monitoring unit detects failure of the employed input clock signal and the switching to a different input clock signal is initiated. The input clock signals are synchronised in phase, with provision of a signal upon phase synchronisation of a replacement input clock signal with a preferred main input clock signal, to allow the switching to the replacement input clock signal.
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申请公布号 |
DE19714468(A1) |
申请公布日期 |
1998.12.24 |
申请号 |
DE19971014468 |
申请日期 |
1997.04.08 |
申请人 |
SIEMENS AG, 80333 MUENCHEN, DE |
发明人 |
MARGGIS, ATHANASE, DIPL.-ING., 80634 MUENCHEN, DE |
分类号 |
G06F1/10;H03L7/081;H04J3/06;(IPC1-7):H04L7/08;H04L5/22 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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