发明名称 Output logic setting circuit in semiconductor integrated circuit.
摘要 An output logic setting circuit includes a fusible fuse element (8) which is selectively rendered conductive or disconnected by external signal operation. The output logic setting circuit is designed to output, from an output terminal (10), an output logic set when the fuse element (8) is rendered conductive or disconnected. The output logic setting circuit includes an inverter circuit (102) which is arranged between the fuse element (8) and the output terminal and has a threshold larger than a predetermined value. <IMAGE>
申请公布号 EP0886381(A1) 申请公布日期 1998.12.23
申请号 EP19980250184 申请日期 1998.05.28
申请人 NEC CORPORATION 发明人 MATSUSHITA, HIROSHI
分类号 H01L21/82;H03K19/003;H03K19/173 主分类号 H01L21/82
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