SEMICONDUCTOR MEMORY

摘要

A semiconductor memory which permits a redundancy memory cell to be disposed in the center while keeping the continuity of the layout unit of a direct peripheral circuit and the overall yield of the memory cell and the direct peripheral circuit to be improved. The semiconductor memory is a 64 Mbit or 256 Mbit DRAM having a hierarchical word line arrangement and a multidivided bit line arrangement and comprises a main row decoder region a main word driven region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a subword driver region, and an intersection region, all formed on a semiconductor chip. The memory cell array (15) comprises redundant memory cells for word and column systems arranged substantially in the center in the word line direction and the bit line direction with respect to a regular memory cell. The direct peripheral circuits of a subword driver adjacent thereto and sense amplifier also comprise redundant cells arranged in the center while keeping a normal repetition unit.