发明名称 DECODER
摘要 <p>PROBLEM TO BE SOLVED: To simplify the configuration of a decoder having provision for a large number of the kinds of image formats. SOLUTION: In the case of writing data to either of 1st and 2nd video signal memories 25, 26, data are read from the other memory. Data are written according to an image rate, and data are read according to a frame frequency. The switching of the 1st and 2nd video signal memories 25, 26 is conducted by using a write end detection circuit 21 that detects it such that the data write is completely finished. The write end detection circuit 21 detects the end of data write by counting the number of data to be written in the 1st or 2nd video signal memories 25, 26.</p>
申请公布号 JPH10336595(A) 申请公布日期 1998.12.18
申请号 JP19970147864 申请日期 1997.06.05
申请人 MITSUBISHI ELECTRIC CORP 发明人 YAZAWA HISANOBU;HOSOYA SHIRO;MATSUO NATSUKO
分类号 H04N5/46;H04N7/01;H04N19/00;H04N19/423;H04N19/44;H04N19/625;H04N19/85;(IPC1-7):H04N7/01;H04N7/24 主分类号 H04N5/46
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