TEST PATTERN GENERATING CIRCUIT OF IC TEST DEVICE

摘要

PROBLEM TO BE SOLVED: To prevent the number of effective channels of a tester from being reduced as in a pin multiplex system and also prevent such a trouble that the increased amount of bits becomes wasteful at the time of simple waveform generation and low speed test from occurring because of a variety of waveform generations and high speed test as in the system in which the number of one word/pin bits of pattern data per test cycle. SOLUTION: Pattern data N=8 words (1 word is m=3 bits) output from a pattern memory 2 in parallel with each other are input into a parallel/series conversion circuit 3. Also a circuit 3 is so structured that it can be switched over by a mode control signal MC between a series output mode (MC='0') in which 1 word/pin data is output in series for each test cycle and a parallel/ series output mode in which n=2 words/pin parallel data (m×n bits) is output in series for each test cycle.