| 摘要 |
<p>PROBLEM TO BE SOLVED: To suppress the tunneling between bands during the erasing operation of a flash memory having a triple well structure, in order to reduce fluctuation of erasing operation. SOLUTION: This memory is a memory cell of the floating gate structure in which formed on a first conductivity type semiconductor substrate 1. The memory cell is arranged, for each erasing unit, in the area having a second conductivity type deep well 2 formed on the semiconductor substrate 1 and a first conductivity type shallow well 3 formed in the deep well 2. Consequently, the potential of the control gate terminal G is set to GND (ground potential) and the potential of source terminal S is set to VPP (first positive potential). Accordingly, the erasing operation for releasing electrons from the floating gates 71, 73 is conducted by utilizing the tunnel phenomenon. In this case, the erasing operation procedures include the first operation to impress VCC (second positive potential) to the wells 2, 3 at the time t1, and the second operation to impress VPP to the source terminal S at the time t2 after the constant period from the time t1.</p> |
