| 摘要 |
<p>PROBLEM TO BE SOLVED: To optimize both performance and chip area by utilizing a cache memory with a built-in CPU core as a memory for storing a program and data. SOLUTION: This CPU core inputs external signals mode for instructing whether to use the cache memory 103 as a cache or to use it as a normal memory for storing the program and the data to a selector 108. When the external signals mode indicate that the cache memory 103 is to be used as the normal memory for storing the program and the data, an address decoder 105 decodes address signals outputted from a CPU main body 101, and in the case of matching with an address for which the normal memory is mapped, a timing control circuit 110 outputs control signals so as to access the cache memory 103 as the normal memory. Thus, the cache memory 103 is accessed as a high-speed memory.</p> |
