Speichertesteinrichtung

摘要

PCT No. PCT/JP97/03464 Sec. 371 Date May 28, 1998 Sec. 102(e) Date May 28, 1998 PCT Filed Sep. 29, 1997 PCT Pub. No. WO98/14954 PCT Pub. Date Apr. 9, 1998A circuit arrangement of a memory testing apparatus provided with a mask pattern memory is simplified. A mask pattern data read out of a mask pattern memory 111 is directly fed to a mask circuit 113 without converting the bit arrangement of the mask pattern data into a bit arrangement conforming to the arrangement of terminals of a memory under test 200. Temporary failure data having a bit arrangement corresponding to the arrangement of terminals of the memory under test is applied from a logical comparator 107 to a failure data selector 108 which controls the passage of a failure data the bit arrangement of which has been converted into a bit arrangement according to a given sequence of bit significance. Failure data having passed through the failure data selector is applied to the mask circuit which functions to mask writing of failure data in a failure analysis memory 109.