New ROM with multiple intersecting conductor line levels

摘要

A novel ROM has intersecting conductor line levels (1, 2, 3), the intersections having either an electrical contact or no electrical contact for defining logic states. Also claimed is production of the above ROM by: (a) deposition, photo-structuring and etching of a metal or polysilicon layer to form conductor lines; (b) deposition of an inter-poly-dielectric and chemical-mechanical polishing to form a smooth surface; (c) production of vias by a photo-technique and subsequent etching; (d) production of a tunnel oxide on the circuit lines in the vias; (e) filling of the vias with via plugs; (f) deposition and structuring of a further metal or polysilicon layer; and (g) repetition of steps (b) to (f) at least once. Also claimed is a method of operating the above ROM in which a selected cell of the ROM is read, the method comprising applying a voltage V1 (preferably -2 V) to one circuit line of the selected cell, applying a voltage V3 (preferably +2 V) to the other conductor line of the cell and applying a voltage V2 (preferably 0 V) to all other conductor lines, the voltage V1 being smaller than voltage V2 and the voltage V2 being smaller than voltage V3.