发明名称 |
Phasenkomparator |
摘要 |
Apparatus for transfer of data between devices having different clock frequencies includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus, and a means for correcting errors in memory. Also included are a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibiting transfer of data fed to a recirculating state device. The apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals. <IMAGE> <IMAGE> |
申请公布号 |
DE69322068(D1) |
申请公布日期 |
1998.12.17 |
申请号 |
DE1993622068 |
申请日期 |
1993.12.30 |
申请人 |
DIGITAL EQUIPMENT CORP., MAYNARD, MASS., US |
发明人 |
HAWKINS, THOMAS B., BOYLSTON, WORCESTER, MASSACHUSETTS 01505, US |
分类号 |
G06F1/12;G06F11/00;G06F11/10;G06F11/16;G06F11/20;G06F11/22;G06F13/28;G06F13/42;H03D13/00;H03L7/085;H03L7/087;H03L7/089;(IPC1-7):G06F11/16 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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