| 摘要 |
Data processing apparatus for executing successive data processing instructions comprises a processing core having a current operational state selected from a predetermined set of possible operational states, the current operational state being defined by a control state signal supplied to the core; a synchronous state machine circuit for generating an output state signal, indicating a provisionally valid next operational state of the core, in response to a predetermined phase of a current clock cycle of a clocking signal, the output state signal being dependent upon a current operational state of the core and control signals generated by the core before the predetermined phase of the current clock cycle indicative of a next data processing instruction to be executed by the core; and an asynchronous logic circuit for generating the control state signal in response to the output state signal and late control signals received after the predetermined phase of the current clock cycle. |
