发明名称 Method for fabricating a nested capacitor
摘要 A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method includes forming a first TEOS layer, a polysilicon layer and a second TEOS layer over the semiconductor substrate. A window is formed through the second TEOS layer to expose a portion of the polysilicon surface. Defined by a first dielectric spacer in the window, the polysilicon layer is etched to expose a portion of the first TEOS layer. The second TEOS layer and the exposed portion of the first TEOS layer are then removed to form a trench extending down to the semiconductor substrate. A polysilicon plug is filled in the trench and a first polysilicon spacer is formed around the first dielectric spacer. A lower electrode including the polysilicon plug, the polysilicon layer and the first polysilicon spacer is therefore formed by removing the first dielectric spacer. Moreover, a dielectric layer and an upper electrode are formed over the lower electrode.
申请公布号 US5849617(A) 申请公布日期 1998.12.15
申请号 US19970881753 申请日期 1997.06.24
申请人 POWERCHIP SEMICONDUCTOR CORP. 发明人 WU, SHYE-LIN
分类号 H01L21/02;H01L21/8242;H01L27/108;(IPC1-7):H01L21/824 主分类号 H01L21/02
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