| 摘要 |
Bit lines coupled to a column of SRAM core cells in an array are sensed asynchronously using zero DC power with either differential sense amplifiers or single-ended amplifiers, according to the present invention. The differential sense amplifier embodiment includes a pair of cross-coupled series-connected PMOS and NMOS transistors connected between the power supplies. Each bit line is coupled to an NMOS gate in the transistor pair, and each PMOS gate is coupled to the drain-source connection of the other series-connected PMOS-NMOS pair. The PMOS gates and PMOS-NMOS drain-source connections define the sense amplifier complementary output signals, whose states are determined by the bit line states. The single-ended embodiment is implemented as a PMOS-NMOS transistor pair inverter connected between the power supplies. Each inverter input is coupled to a bit line, and the inverter outputs are the sense amplifier outputs. In both embodiments, series-connected PMOS-NMOS pairs do not provide any DC path and function asynchronously without clock or enabling signals other than the bit line signals. In either embodiment, a zero DC power consumption bit-line clamp implemented as a PMOS-NMOS inverter is also coupled to each bit line, and is controlled by the associated sense amplifier output signal. The bit-line clamp forces an associated bit line to a full "1" or "0" logic state.
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