| 摘要 |
A method of constructing a planar equal path length clock tree. Prior computer-generated methods of creating low-skew clock trees required that clock sinks be uniformly distributed throughout the circuit. Moreover, the tree produced would often be non-planar, thus increasing layout design complexity and cost. The present invention provides for a method of automatically producing a planar clock tree with equal path lengths from each clock sink to the clock source. A first branch wire is formed between the clock source and the clock sink that is a farthest distance from the clock source. Thereafter, the remaining uncoupled clock sinks are coupled to the clock tree according to a maximum rule and a minimum rule. Thus a planar equal path length clock tree is formed. The planar equal path length clock tree is transformed in to a rectilinear clock tree, including horizontal and vertical wires, by using a line search algorithm. The rectilinear clock tree may then be optimized for tolerable clock skew by a cut-and-link method.
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