发明名称 INTEGRATED CIRCUIT LAYOUT SYNTHESIS TOOL
摘要 <p>A design-rule driven IC layout synthesis tool which generates IC layouts using non-orthogonal geometry is provided. First, a physical ordering of a set of IC devices to be included in the IC layout is determined based upon predetermined electrical connections between the IC devices. Then, one or more IC device groups are established based upon the physical ordering of the set of IC devices. An IC device group layout is generated for each of the one or more IC device groups based upon predetermined design criteria. Generating a device group layout involves evaluating a series of layout solutions for the device group and then determining an optimal layout solution based upon a cost function. Then, a relative physical arrangement of the IC device group layouts is determined based upon predetermined routing criteria. Finally, connections are determined between the IC device group layouts based upon the predetermined electrical connections between the devices.</p>
申请公布号 WO1998055950(A1) 申请公布日期 1998.12.10
申请号 US1998010276 申请日期 1998.05.20
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