| 摘要 |
<p>A circuit for receiving data comprises a first receiver means (6) having input means (6a) for receiving said data and an input (6b) for receiving a first clock signal (CLK2), whereby said data is clocked into said first receiver means by said first clock signal. The circuit also has a second receiver means (8) having input means (8a) for receiving said data and an input (8b) for receiving a second clock signal (_CLK2), said first and second clock signals (CLK2, _CLK2) having the same frequency and being phase shifted with respect to one another, whereby said data is clocked into said second receiver means (8) by said second clock signal. Determining means (12, 14) are provided for determining if at least one of said receiver means has correctly received said data. Means for selectively enabling a first output of one of the receiver means is provided in accordance with the determination made by said determining means.</p> |
