DIGITAL DELAY LOCK LOOP

摘要

A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may comprise a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses (U and D) control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2x clock signal. The 2x clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop to stabilize after a few clock cycles without additional external control. The use of digital delay elements in the delay lock loop eliminates the need for large analog circuits used in PLLs, and thus saves silicon (wafer) space. In addition, the digital circuitry of the present invention consumes less power than a comparable analog PLL. Moreover, the circuit of the present invention will lock at phase quickly. The digital design of the present invention may also be less sensitive to technology type (i.e., types of digital design) and thus be transitioned to future designs with less debugging and the like.