Power on reset signal generation circuit

摘要

The reset signal generation circuit provides a reset signal signalling switching in of the supply voltage. The circuit nodes (VB,VC) have a potential which affects the duration and/or amplitude of the reset signal, which is coupled via capacitive elements (C2,C3) for initial discharge and/or parasitic capacitance compensation, to the supply voltage terminals. An inverter (I1) is coupled between a first supply terminal (VSS) and one circuit node (VA), with its input coupled to a second circuit node (VB) and its output coupled to a third circuit node (VC), with an initialising circuit (INIT) between both supply terminals (VDDx,VSS).