发明名称 PLANARIZATION TECHNIQUE FOR DRAM CELL CAPACITOR ELECTRODE
摘要 PROBLEM TO BE SOLVED: To provide a DRAM forming method which enables high productivity and high reliability. SOLUTION: A silicon nitride etch stopping layer 90 is bonded onto an entire structure of a device, including first and second source/drain regions 80 and 84 which have been exposed during a spacer etch process, followed by further bonding of a thick oxide layer 96 thereon. By performing chemicomechanical polishing, the surface of the thick oxide layer 96 is planarized. An opening is formed in the thick oxide layer 96 above the first source/drain region 84 so as to be stopped by the etch stopping layer 90. Thereafter, the etch stopping layer 90 within the opening of the thick oxide layer 96 is removed to form a capacitor electrode 98 therein, so as to be in contact with the exposed portion of the first source/drain region 84. Similarly, a bit line contact for the device may be formed.
申请公布号 JPH10321814(A) 申请公布日期 1998.12.04
申请号 JP19970121242 申请日期 1997.05.12
申请人 UNITED MICROELECTRON CORP 发明人 SON SEII;YU SUIYO
分类号 H01L21/3205;H01L21/306;H01L21/336;H01L21/8242;H01L27/108;H01L29/78 主分类号 H01L21/3205
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