| 摘要 |
PROBLEM TO BE SOLVED: To enable high speed writing operation of static RAM, etc., while reducing the required layout area of a writing circuit by providing a switch means, which is selectively turned ON depending on the write data, between the non-inverting and inverting signal lines of complementary bit lines and the ground potential of the circuit. SOLUTION: A unit write circuit UWC0 provides in series the N-channel MOSFETQ28, Q29, Q30, Q31 between the non-inverting and inverting signal lines of the complementary bit lines B0 to B7 of the corresponding sub-memory array. Among these MOSFETs, an inverting signal from an inverter N37 of an output signal of NAND gate NA14 is supplied in common to the gate of FETQ28. An output signal of the NAND gate NA14 is selectively set to the low level when the predecoded signal and inverted write signal are set to the high level. Thereby, the corresponding FETQ28 is selectively turned ON. |
