发明名称 TRELIS DECODING SYSTEM
摘要 PROBLEM TO BE SOLVED: To simplify the structure of the system and to reduce a time required for decoding by allowing the decoder to support both a 8-state mode and a 16-state mode and using one decoder only in time division in place of 12 decoders of a conventional system. SOLUTION: In the case that received trelis code data indicate the 8-state mode, a segment synchronizing signal elimination filter 1 passes the trelis code data as they are in response to a mode selection signal FENA, and in the case that the received trelis code data indicate the 16-state mode, the segment synchronizing signal elimination filter 1 eliminates the effect of a segment synchronizing signal and provides an output of a symbol to be decoded. A BMU 2 outputs 7 branch metrics BM1-7 in the case of the 8-state mode and outputs 15 branch metrics BM1-15 in the case of the 16-state mode. An ACS 3 receives the mode selection signal FENA and all branch metrics from the BMU 2 and selects a path with a highest probability among many path metrics.
申请公布号 JPH10322229(A) 申请公布日期 1998.12.04
申请号 JP19980120508 申请日期 1998.04.30
申请人 DAEWOO ELECTRON CO LTD 发明人 SHO KATSUKEN
分类号 H04N19/00;H03M13/23;H03M13/25;H03M13/39;H04L1/00;H04N7/015;H04N19/102;H04N19/117;H04N19/134;H04N19/196;H04N19/42;H04N19/44;H04N19/46;H04N19/635;H04N19/70;(IPC1-7):H03M13/12;H04N7/24 主分类号 H04N19/00
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