| 摘要 |
The invention relates to a device for clock recovery and regeneration of data of HDB3 coded data signals, comprising a device (3) for dividing the data signal (DS) into two channels (DS1,DS2), a theshold value decision circuit device (7) to which the data signals are supplied on both channels and which generates data signals with two logical states (low/high), a scanning device (11) for scanning signals from the threshold value decision circuit device (7) with a system clock (ST) and a decoder device (15) to decode the coded data signal. The invention is characterized in that a timing device (13) is provided to generate an enable-signal (ES) when the signal edge rises and generates an enable-signal (ES) when no signal edge is present after three predeterminable clock counts, in addition to linking both data signals to an output signal, which is supplied to the decoder device (15). The invention also relates to a method enabling clock recovery and data retiming of HDB3 coded data signals. |
