Semiconductor memory element e.g. for DRAM

摘要

The semiconductor memory element (22) is accessed by the outputs of a line decoder (21) address. The decoder accesses a word line and outputs are received by an amplifier circuit (23). The outputs are latched in two independent circuits (26',26'') via a switching block (27). The column address is handled by a decoder (24) that controls the latch circuits and these deliver output to a bus amplifier.