| 摘要 |
<p>When a data bus is separated from a CPU (1) and a transmission ready signal (TXRDY) becomes active, a DMA control circuit (10) collectively reads 32-bit data according to a first address in a DRAM (2) wherein the data is stored and an address width which are set by the CPU (1), and then stores the data in a transmission buffer (16). Then, a selector (17) selects the data in units of 8 bits from the transmission buffer (16) and then a selector (17) writes the selected data in a communication circuit (14) and, after that, the bus release request is cancelled. When a transmission ready signal is given again, the same processing is repeated.</p> |
