发明名称 |
DISTRIBUTED LOGIC ANALYZER FOR USE IN A HARDWARE LOGIC EMULATION SYSTEM |
摘要 |
A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
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申请公布号 |
WO9854649(A1) |
申请公布日期 |
1998.12.03 |
申请号 |
WO1998US10312 |
申请日期 |
1998.05.18 |
申请人 |
QUICKTURN DESIGN SYSTEMS, INC. |
发明人 |
SAMPLE, STEPHEN, P. |
分类号 |
G01R31/28;G01R31/3177;G01R31/3185;G06F11/22;G06F11/25;(IPC1-7):G06F11/25;G01R31/318 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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