| 摘要 |
An apparatus for L pixel data corresponding to 1 line inputted from a memory section to an upper and a lower address electrode driving sections of a flat display (eg a plasma display), respectively in response to a control signal supplied from a timing control section, is disclosed. The data interfacing apparatus comprises upper and lower data interfacing sections, and an input/output control section. The upper and the lower data interfacing sections includes a couple of temporality storing sections comprising a storing area for temporarily storing L/2 pixel data, an input selecting section for inputting 3N pixel data into the storing area over M (where M is a least integer which is greater than quotient of L divided by 3N) times in response to M input selecting control signals which are sequentially generated, and an output selecting section for outputting the L/2 pixel data stored in said storing area by P units over Q {= (L/2)/P} times in response to Q output selecting control signals which are sequentially generated, respectively. The input/output control section includes a first control signal generating section for receiving a first clock signal and a first reference signal from the timing control section and for generating the M input selecting control signals by shifting the first reference signal over M times in response to the first clock signal, a second control signal generating section for receiving a second clock signal and a second reference signal from the timing control section and for generating the Q output selecting control signals by shifting the second reference signal over Q times in response to the second clock signal, an operation mode control section for providing the control signal from the first and the second control signal generating sections to the couple of temporality storing sections for a data input/output mode to be alternately executed in the couple of temporality storing sections in response to an input/output mode control signal. As a result, a line pattern between the data interfacing section and the timing control section is simplified. |
