发明名称 |
Test circuit and method for refresh and descrambling in an integrated memory circuit |
摘要 |
A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.
|
申请公布号 |
US5844914(A) |
申请公布日期 |
1998.12.01 |
申请号 |
US19970850807 |
申请日期 |
1997.05.02 |
申请人 |
SAMSUNG ELECTRONICS, CO. LTD. |
发明人 |
KIM, HEON-CHEOL;JUN, HONG-SIN;CHO, CHANG-HYUN |
分类号 |
G11C11/401;G01R31/28;G01R31/3181;G11C11/406;G11C29/08;G11C29/12;G11C29/18;(IPC1-7):G06F11/00 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|