Fast verify for CMOS memory cells

摘要

A method of verifying functionality of a circuit including an array of CMOS memory cells, each memory cell including: an NMOS transistor and a PMOS transistor having a common floating gate and drains connected together to form an output; a control capacitor having a first terminal connected to the common floating gate; a first transistor having a source to drain path connecting a second terminal of the control capacitor to a control gate (CG) node and having a gate forming a wordline (WL) node; and a tunneling capacitor connecting a write control (WC) node to the common floating gate, wherein a row of memory cells in the array have CG nodes connected together and wherein a column of memory cells in the array have CG nodes connected together, the method including the steps of: (a) programming all memory cells in a selected row (b) applying VVER ( APPROX 1.8V) to the CG and WC nodes of the cells in the selected row while applying a voltage VVER+ (VVER plus an NMOS threshold) to WL nodes; (c) raising the WL nodes of selected cells in the selected row to VMUXVER+ (VMUXVER+ being VMUXVER or APPROX 6V plus an NMOS threshold); (d) lowering the WL nodes of unselected cells to VVER+; and (e) raising the CG nodes of the selected cells to VMUXVER so that selected cell outputs go low . Once functional verification is performed with selected cells as chosen in steps (a-e), the selected cells are charged and steps (b-e) are repeated until all desired patterns of cells in the selected row have been selected in a functional verification process. Steps (a-e) are then repeated for a next selected row. The process of the present invention enables toggling the output of the selected cells from a programmed or low state to a high state without requiring that the selected cell be reprogrammed.