| 摘要 |
An architecture and method for communicating between multiple processors. In one embodiment, first data is transferred from a first processor into a first memory. In the present embodiment, multiplexing circuitry connects the first processor to the first and second memories, but the first processor only has access to the first memory. Similarly, second data is transferred from the second processor into the second memory. Multiplexing circuitry connects the second processor to the first and second memories, but the second processor only has access to the second memory. In the present embodiment, the multiplexing circuitry switches the connection between the first processor and the first and second memories and the second processor and the first and second memories. In so doing, the first processor is switched from having access only to the first memory to having access only to the second memory. Likewise, the second processor is switched from having access only to the second memory to having access only to the first memory. Next, the second data is transferred from the second memory into the first processor such that the first processor receives the second data previously transferred into the second memory by the second processor. Similarly, the first data is transferred from the first memory into the second processor such that the second processor receives the first data previously transferred into the first memory by the first processor. In such a manner, the present invention provides for communication between multiple processors.
|
