发明名称 Address lines load reduction
摘要 Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.
申请公布号 US5845098(A) 申请公布日期 1998.12.01
申请号 US19960669680 申请日期 1996.06.24
申请人 MOTOROLA INC. 发明人 GALANTI, DAVID;ZMORA, EITAN;BARON, NATAN;KLOKER, KEVIN
分类号 G06F13/42;(IPC1-7):G06F13/40 主分类号 G06F13/42
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