发明名称 |
Redundanzspeicherzellen mit Parallelprüffunktion enthaltendes Halbleiter-Speichergerät |
摘要 |
In a semiconductor memory device which can perform a parallel test upon a predetermined number of memory cells by using a degenerate address (X0-X9, Y3-Y10) of a plurality of first addresses each corresponding to one memory cell, when a defective memory cell is found by a parallel test using the degenerate address, an address whose space includes the space of the degenerate address is written into only one location of its corresponding redundancy decoder to replace the defective memory cell with its corresponding redundancy memory cell. <IMAGE> |
申请公布号 |
DE69321623(D1) |
申请公布日期 |
1998.11.26 |
申请号 |
DE1993621623 |
申请日期 |
1993.01.27 |
申请人 |
NEC CORP., TOKIO/TOKYO, JP |
发明人 |
KAGAMI, AKIHIKO, MINATO-KU, TOKYO, JP |
分类号 |
G11C11/401;G11C29/00;G11C29/04;G11C29/34;(IPC1-7):G06F11/20 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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