Semiconductor integrated circuit with test mode and normal-mode operation current paths

摘要

A test-target circuit is constructed of circuit blocks each comprising low-Vt MOS transistors including address buffers and a timing generator. A test enable signal for indication of a test, an operation selection signal for indication of an operation, and a block selection signal used to select a desired circuit block are provided. A high-Vt NMOS and a high-Vt PMOS transistor are provided in order to provide to a test circuit one of detected currents of the circuit blocks that was selected by placing a block selection signal and the test enable signal in the state of HIGH. <IMAGE>