发明名称 |
Bit-line precharge current limiter for CMOS dynamic memories |
摘要 |
The memory comprises several word-lines and complementary bit-line pairs. A source of precharge voltage for precharges the complementary bit-line pairs. Several precharge equalisation circuits each of which comprises three field effect transistors. The one FET is connected across a corresponding complementary pair of bit-lines and the other two FET's are connected in series with a respective complementary pair of bit-lines. The gates of each of the FET's are connected to receive a precharge equalisation control signal. The precharge equalisation circuits is connected to the source of the precharge voltage. One precharge equalisation circuit precharges each of the complementary bit-line pairs. A current limiter limits the precharge current flowing into the complementary bit-line pairs to a precharge current limit value. The current limiter comprises a FET which is biased to limit current flow through the transistors to the precharge current limit value. |
申请公布号 |
EP0732701(A3) |
申请公布日期 |
1998.11.25 |
申请号 |
EP19960480016 |
申请日期 |
1996.02.06 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KIRIHATA, TOSHIAKI;WATANABE, YOHJI;FUJII, SHUSO |
分类号 |
G11C11/409;G11C11/401;G11C11/4094;G11C29/04;(IPC1-7):G11C11/409 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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