Variable delay circuit, ring oscillator, and flip-flop circuit

摘要

In a variable delay circuit for delaying an input signal by a variable delay time from a rising edge or a falling edge of the input signal to a rising edge or a falling edge of an output signal in a digital circuit, the variable delay circuit comprises a data signal input terminal (I1); a first signal input terminal (VL) to which a low-level signal of a logic gate is applied; n pieces of selector circuits (SEL1 to SELn) (n = integer larger than 0) selecting either the signal at the data signal input terminal (I1) or the signal at the first signal input terminal (VL) in response to signals from first selector signal input terminals (S1 to Sn); and an (n+1)-input NOR circuit (NOR2) to which the signal at the data signal input terminal (I1) and output signals from the selector circuits (SEL1 to SELn) are applied. In this variable delay circuit, a delay time shorter than the delay time of a single-stage buffer circuit can be controlled by only digital circuits.