| 摘要 |
Test results of a memory in which an array of memory cells in the memory is different from a bit array of data read out thereof are written in a failure analysis memory in an array close to the array of the memory cells in the memory. An address scrambler capable of arbitrarily rearranging a bit array of an address signal to be supplied to a memory under test is provided, and an altered address signal a bit array of which is altered by the address scrambler is supplied to a failure analysis memory and the pass/failure judgment results of the memory cells in the memory under test are written in the failure analysis memory at an address space thereof having a structure close to the array structure of the memory cells in the memory under test.
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