| 摘要 |
A circuit design tool which includes an architecture for a multiplier which is faster and more compact than known multipliers through the use of Wallace trees, the elimination of Dadda nodes along the critical paths, the placement of half-adders at an initial pat of the Wallace tree, the replacement of low-order terminating adders with ripple-carry adders, and the replacement of high-order terminating adders with carry-select adders.
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