发明名称 Method and apparatus for screening integrated circuit chips for latch-up sensitivity
摘要 Integrated circuit chips are screened for susceptibility to latch-up by first applying power and ground to the chips to be tested while limiting current flow to a non-destructive compliance value. Next, the chips are irradiated with a pulse of radiation having an energy dose calibrated to trigger latch-up in latch-up sensitive chips. Upon termination of the radiation, the current is detected. Chips having current persisting at the compliance value are indicated as failing. The current in passing chips returns approximately to the original standby current value. In the preferred embodiment, the radiation is visible light and the radiation energy dose is selected to cause a percentage of chips to latch-up approximating the percentage of failures expected at burn-in.
申请公布号 US5841293(A) 申请公布日期 1998.11.24
申请号 US19950581861 申请日期 1995.12.22
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LEAS, JAMES MARC
分类号 G01R31/28;(IPC1-7):G01R1/04;G01R31/26 主分类号 G01R31/28
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